Digital I/O cards, pattern or pulse generators and digital data acquisition cards are all focused on digital signals. Input and output signals have two logic levels called low state (0) and high state (1). The electrical representation of these logical levels depends on the logic family and the supported I/O standard.
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Different interface types are found for the digital devices as well as for the external devices to connect with. It is important for the correct function of both to check the specification details to see whether both devices fit together or not. All logic families have a defined voltage windows for low state and high state for output and for input where the output window is defined more narrow while the input window accept a wider variation. Showing the specification of the M2p.75xx digital I/O card series with TTL compatible inputs and outputs explains this:
Classic logic families like TTL or CMOS are all single-ended meaning that a single line is carrying the information in relation to a common Ground. Depending on the mechanical structure this ground may be a separate ground for each digital line or a shared ground for all digital lines.
Differential logic families like LVDS have a pair of cables for each digital lines carrying the logic information as differential signal. Using differential signaling allows to use far higher speed.
By Gidget Cathcart, Agilent Technologies
Testing digital designs usually requires one or more digital signals, some of which can be very difficult to generate. Pattern generators are specifically designed to address this problem. Whatever digital stimulus signals are needed to exercise a specific device under test, a pattern generator most likely can provide them. In addition, an engineer can use a pattern generator to integrate digital patterns anywhere in the test sequence, from beginning to end. Pattern generators are also a good fit for applications such as semiconductor electrical testing, where pattern stimulus data is needed for fault testing, and a digital system controller running through user-defined control algorithms. On the software side, a pattern generator can function as a debugging tool for software engineers developing applications for the device under test (DUT).
SOLVING DIGITAL TEST CHALLENGES
In many digital tests, hardware and software
engineers need the ability to generate digital stimuli to simulate infrequently
encountered test conditions in hardware design and software program testing.
One test challenge a pattern generator solves is providing digital stimulus
where the normal digital signals to the device under test are missing. Again,
in semiconductor electrical testing, pattern generators can be used to stimulate
a digital circuit in order to evaluate output responses, which are then compared
to expected responses to determine whether the device is faulty or not.
Digital stimulus may be missing in other applications such as a digital control system. For this application, multiple digital stimuli of varying widths may be required, with enough memory to produce the necessary bit stream patterns. In this case, a pattern generator is appropriate since it can be configured in widths of a byte, word and long word enabling up to 32- or 64-bit channels, depending on the instrument. In addition, if more channels or fanout is needed, additional generators can be connected to the system. In contrast, a function arbitrary-waveform generator with only single-or dual-bit output channels cannot provide the fan out capability needed except at an unreasonable test system cost. Figure 1 shows a conceptual block diagram of the device under test, stimulated by a pattern generator.
Another test challenge, other-than providing the stimulus for the missing digital signals to a device under test, is developing algorithmic bit patterns or vector sets to be downloaded into the pattern generator. A critical consideration the engineer needs to evaluate is the minimum test vector set or bit stream length, which translates into memory depth, to address the appropriate test model and test set for the device under test. Often times, this process takes some time to determine the minimum test vectors needed to test and stimulate the DUT for the desired response(s). In semiconductor electrical testing, these test vectors may come from a software program that uses algorithmic methods or pseudo random generators that can be used for the device, while other methods may be more of a manual task to determine the proper vector test sets.
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In either case, automated or manual, optimization is a factor because this translates into how much pattern memory is needed to generate the patterns. This may be a critical factor in determining whether a specific pattern generator will work for the test vector set it needs to support for the DUT. Sometimes, due to the test vector size and the pattern depth needs, the test(s) may have to be augmented and partitioned into several segments to accomplish the task. Figure 2 shows a conceptual representation of a pattern generator vector test set.
PATTERN GENERATOR FEATURES AND FUNCTIONS
With many pattern generators, you can place a digital circuit or system
in a desired state, operate it at a desired programmable frequency speed, single-step
it through a series of states quickly and loop on a pattern. Some even have
conditional triggering capabilities. Looping may be beneficial if the vector
set is large and if a pattern sequence repeats. A looping option may be the
ideal feature to minimize the vector size of the pattern waveform.
In control systems, conditional triggering is essential for giving a closed loop control action to either start a digital pattern sequencer or stop the sequencer based upon a defined digital system condition or response to another stimulus. Many triggering capabilities are defined as edge triggered or gate triggered giving the test engineer optimal flexibility in matching an application's requirements. Since pattern generators allow for testing at speed as well as troubleshooting faults by stepping through a bit pattern sequence, they are ideal for any test stage of the device under test whether it be early development or final system test.
Pattern generators are also useful for software test. Software debugging often involves emulation software and hardware support for the device under test. Having the ability to download hardware configurations to the DUT for specific device conditional states allows the software engineer to execute commands and algorithms quickly for software verification purposes. You can look ahead for desired states and compare and back track software steps for adjustments. Therefore, where appropriate, pattern generators can be used as simple serial links to download custom device under test configurations for software evaluation and test.
Furthermore, many software enabling tools are available to aid in the test development stage to get the hardware configuration up and running quickly. The tools range from custom proprietary software, standard drivers, front panel display control and even instrument web pages like those available with Agilent Technologies A and LXI LA digital I/O products. These give the user the ability to do quick configuration and exert control of the pattern generator through a web browser, saving valuable time. Figure 3 shows Agilent's web page interface tool.
CONSIDERATIONS WHEN SELECTING A PATTERN GENERATOR
When selecting a pattern
generator, several things must be considered. The following is a list to keep
in mind when evaluating and selecting the pattern generator that best fits your
needs.
SUMMARY
Pattern generators are ideal for digital applications where digital
stimulus signals may be missing to test a specific device under test. The rich
feature sets provided by pattern generators allow an engineer to integrate the
pattern generator anywhere in the test process from the beginning stages to
the final stage of system test. Often times, pattern generators are handy and
a good fit for semiconductor electrical testing, as a digital system controller
running through user defined control algorithms, as well as a debugging tool
for software engineers developing software applications for the device under
test.
ABOUT THE AUTHOR
Gidget Cathcart holds a Bachelor of Engineering
with Electrical Emphasis degree and is a digital hardware design engineer in
Agilent's System Products Division. You can reach her by at [ protected]
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